Dec 12, 2019   3:40 a.m. Otília
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Persons at STU


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Ing. Lukáš Kohútka, PhD.
Identification number: 5813
University e-mail: lukas.kohutka [at] stuba.sk
 
Výskumný pracovník s VŠ vzdelaním - Institute of Electronics and Phototonics (FEEIT)
 
External colleague - Faculty of Informatics and Information Technologies (STU)

Contacts     Graduate     Lesson     Final thesis     
Projects     Publications     Curriculum vitae     Supervised theses     

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The selected person is an author of the following publications.

Ord.PublicationsType of resultYearDetails
1.A new hardware-accelerated scheduler for soft real-time tasks
Kohútka, Lukáš -- Stopjaková, Viera
A new hardware-accelerated scheduler for soft real-time tasks. In MECO 2019. Piscataway: IEEE, 2019, p. 110--113. ISBN 978-1-7281-1739-3.
contributions in anthologies, chapters in monographs/textbooks, abstracts2019Details
2.A on-chip energy harvester system for low voltage applications
Stopjaková, Viera -- Arbet, Daniel -- Nagy, Lukáš -- Kováč, Martin -- Potočný, Miroslav -- Šovčík, Michal -- Rakús, Matej -- Kohútka, Lukáš
A on-chip energy harvester system for low voltage applications. In EUROPRACTICE: Activity report 2018-2019. Heverlee : imec, 2019, p. 51--53.
contributions in anthologies, chapters in monographs/textbooks, abstracts2019Details
3.Automated evaluation of neurophysiological signals
Beňo, Dávid -- Kohútka, Lukáš
Automatizované vyhodnocovanie neurofyziologických signálov. Diploma thesis. 2019.
final thesis2019Details
4.Automatic translation between VHDL and Verilog languages
Štefaňák, Marián -- Kohútka, Lukáš
Automatický preklad medzi jazykmi VHDL a Verilog. Bachelor thesis. 2019.
final thesis2019Details
5.Automatics translation between VHDL and Verilog languages
Orčová, Mária -- Kohútka, Lukáš
Automatický preklad medzi jazykmi VHDL a Verilog. Bachelor thesis. 2019.
final thesis2019Details
6.FPGA-based task scheduler for mixed-criticality real-time systems
Kohútka, Lukáš -- Stopjaková, Viera
FPGA-based task scheduler for mixed-criticality real-time systems. In iCCECE ’19. Piscataway: IEEE, 2019, p. 5--10. ISBN 978-1-7281-2138-3.
contributions in anthologies, chapters in monographs/textbooks, abstracts2019Details
7.Graphical representation of neurophysiological signals
Moravčík, Marko -- Kohútka, Lukáš
Grafická reprezentácia neurofyziologických signálov. Diploma thesis. 2019.
final thesis2019Details
8.Hardware dynamic memory manager for hard real-time systems
Kohútka, Lukáš -- Nagy, Lukáš -- Stopjaková, Viera
Hardware dynamic memory manager for hard real-time systems. Annals of Emerging Technologies in Computing, 3. p. 48--70.
articles in magazines2019Details
9.Low latency hardware-accelerated dynamic memory manager for hard real-time and mixed-criticality systems
Kohútka, Lukáš -- Nagy, Lukáš -- Stopjaková, Viera
Low latency hardware-accelerated dynamic memory manager for hard real-time and mixed-criticality systems. In DDECS 2019. Danvers: IEEE, 2019, ISBN 978-1-7281-0072-2.
contributions in anthologies, chapters in monographs/textbooks, abstracts2019Details
10.Web application for sale a desktop application and license management
Jurík, Juraj -- Kohútka, Lukáš
Webová aplikácia pre predaj desktopovej aplikácie a manažment licencií. Bachelor thesis. 2019.
final thesis2019Details

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