Aug 26, 2019   5:08 a.m. Samuel
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Faculty of Informatics and Information Technologies - list of publications

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ŠTEFAŇÁK, M. -- KOHÚTKA, L. Automatický preklad medzi jazykmi VHDL a Verilog. Bachelor thesis. 2019.

Original name: Automatický preklad medzi jazykmi VHDL a Verilog
English name: Automatic translation between VHDL and Verilog languages
Czech name:
Written by (author): Bc. Marián Štefaňák
Ing. Lukáš Kohútka, PhD.
Department: Institute of Computer Engineering and Applied Informatics
Institute of Electronics and Phototonics
Kind of publication: final thesis
University: -
Type of work: Bachelor thesis
Place of publishing:
Year of publication: 2019
Number of pages:
Original language: Slovak
Description in original language:
Description in English:
Description in Czech:
Key words: slovak: VHDL, automatic translation, automaticky preklad, SystemVerilog
Year of submission: 2019
Year of transmission:
Entry made by: Bc. Marián Štefaňák
Last change: 06/22/2019 22:23 (Data import from library)