Dec 12, 2019   6:19 a.m. Otília
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Cryptographic Algorithms and Primitives with Increased Resistance Against Side - Channel Attacks

Supervisor: prof. RNDr. Otokar Grošek, PhD.

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Project description:The cryptographic modules (hardware or software) can be attacked on two levels: l) on the algorithmic level (using the methods of the linear and differential cryptanalysis) and 2) on the implementation level (using passive and active attacks based on information leakage by so called side chaririels: power consumption, time, electro-magnetic interference, etc. or fault injection modifying the algorithm behavior). Current cryptographic algorithms are designed in a way that they are practically not attackable using currently available computing power. However, it has tumed out that the systems can be easily attacked using side channels. The methods using power analysis and electro-magnetic emanation are considered as the most powerful and the most dangerous attacks, because they need only relatively simple measuring equipment and a limited access to the attacked device. The current research in the field of countermeasures against side-channel attacks is oriented exclusively at securing existing cryptographic algorithms that have not been designed having the information leakage in mind. Securing of existing algorithms is often very expensive (in term of the occupied area) and it slows down the algorithm execution. In some logic devices some securing techniques are not feasible because of existing technology constraints. The main aim of the project is to study the cryptographic primitives composing cryptographic algorithms from the point of view of side-channel attacks and to propose a modification of existing algorithms or to propose new algorithms that will be intrinsically resistant against side-channel attacks and especially power analysis attacks. This way, the proposed methods should not need additionallogic area for implementing counter-measures against side-channel attacks. The robustness of the proposed solutions will be evaluated mathematically and in hardware modules based on reconfigurable logic devices (FPGAs).
Kind of project:Bilaterálna spolupráca - SR - Francúzsko ()
Department:Department of applied informatics and information technology (FEEIT)
Project identification:SK-FR-0011-09
Project status:Successfully completed
Project start date :04. 01. 2010
Project close date:20. 12. 2011
Number of workers in the project:2
Number of official workers in the project:0